[nanoPost] nano-CMOS devices

University UK

The silicon microelectronics industry has entered in 2000 the nanotechnology era with sub 40 nm transistors in mass production in the 90 nm technology node. This is now the largest nanotechnology industry in terms of revenue and profits.

The group is one of the largest and internationally leading specialised semiconductor device modelling groups focused on the modelling and simulation of nano-CMOS devices and nano biological molecules and systems. In recent years we have led both the commercial players and other major international research groups, in developing a unique 2D finite element Monte Carlo compound semiconductor device simulator suitable for HEMTs with nanoscale dimensions.  We are one of the few groups worldwide with in-house full-band 2D/3D ensemble Monte Carlo simulation for advanced nano_CMOS devices. We are recognised as world leaders in the simulation of intrinsic fluctuations in nano-CMOS dveices introduced by the discreteness of charge and atomicity of matter and the study of their impact on the yield and the reliability of circuits and systems.

It is now widely recognised that intrinsic parameter fluctuations include random discrete dopants, line edge roughness and oxide thickness fluctuations. represent major challenges to scaling and integration for the present and next generation of nano-CMOS transistors and circuits. We have the best in the world tools to simulate these effects and to optimise the design of the next generations nano-CMOS devices. We see significant potential in:

1) Providing simulation services of nano-CMOS devices to the above and similar companies.
2) Commercialisation of some of the nano-CMOS simulation tools available in the group.

Intrinsic parameter fluctuations and their impact on circuit/system design
An important problem which already affects the design of next generation analogue, digital and mixed signal circuits (and which acts as a specific example of the interesting research areas at the interface of device and circuit design noted above) is the ever increasing magnitude of intrinsic parameter fluctuations introduced by the discreteness of charge and matter in the next generation nano-CMOS devices independent of architecture.
 
3D simulation of a 3535 nm FET featuring random discrete dopants. The potential distribution is colour mapped. Potential fluctuations in the channel associated with the dopant distribution result in different characteristics for each device. Set of ID-VG characteristics for an ensemble of 200 macroscopically identical but microscopically distinct 3030 nm MOSFETs. Differences result from varying numbers and positions of dopants within the active region of each transistor. Distribution of static noise margins in SRAM cells assembled using an ensemble of 200 distinct 3030 nm FETs. Only cells with a cell ratio larger than 3 achieve 90% yield in 1Mbit systems.

As illustrated above, variations in the number and position of dopants, make even contemporary MOSFETs microscopically different, introducing significant parameter variations from device to device. In addition, the trapping of a single electron in the channel region can change device ID by over 100%. Interface roughness on the order of 1-2 atomic layers and related local variations in the oxide/body thickness introduce variations in gate tunnelling, quantum confinement and mobility between devices. The granularity of gate materials and the photo-resist introduce unavoidable line edge roughness (LER) in the gate pattern definition and variations in device geometry. New materials such as high- dielectrics and SiGe are predicted to exacerbate these variations. All these effects introduce intrinsic parameter fluctuations whose magnitude increases as devices shrink, and will increase dramatically as CMOS scales to nanometer dimensions. Contrary to the device parameter variations introduced by well understood processing deviations, these intrinsic parameter variations cannot be controlled by improving the fabrication technology.
Intrinsic parameter fluctuations will have a crucial impact on the functionality, yield and reliability of both analogue and digital circuits and systems. They already affect the scaling of SRAM cells, at a time when absolute noise margins are shrinking due to continued supply voltage reduction. Pictured above are random dopant induced distributions of static noise margin (SNM) in an ensemble of SRAM cells of various cell ratios, for devices in the advanced stages of the 90 nm technology node. To obtain acceptable yield in the presence of such fluctuations, the cell ratio of the circuit must be increased from W/L=1 to W/L=3.
The problems introduced by intrinsic parameter fluctuations are well understood and under active research by large semiconductor players like Intel, Motorola/Freescale and IBM, but not widely advertised, and not well appreciated by the design community – particularly in the UK. As a leading international player in the simulation and understanding of the various sources of intrinsic parameter fluctuations in nano-CMOS, the Device Modelling group at Glasgow is funded, not only by EPSRC and EC, but also by IBM, Freescale, Toshiba and Fujitsu – all in this specific area. This creates an opportunity for collaboration with Cadence in order to obtain an early quantitative and qualitative appreciation of the implications of intrinsic parameter fluctuations on the next generation circuits and systems. The research activities at the interface between the device and the circuit/system modelling and simulation might include.
• Comprehensive physical simulations in order to understand the source and the magnitude of intrinsic parameter fluctuations in transistors with conventional and novel device architectures to the end of the roadmap, and beyond.
• Development of compact model and parameter extraction strategies which capture intrinsic parameter fluctuation effects and can be used in circuit and system simulations.
• Studying the impact of the intrinsic parameter fluctuations on circuit building-blocks and systems and understanding at which technology node they will be prohibitive for particular components design.
• Development of intrinsic parameter fluctuations resistant architectures including concepts like, redundancy, self-organisation, self-healing and random logic.
• Developing circuit concepts and architectures that could benefit from the presence of intrinsic parameter fluctuations (for example neural network based computing, pattern recognition and control).